1. Field of the Invention
The present invention relates generally to the field of computer memory, and more particularly, to a dynamic random access memory single in-line memory module.
2. Related Art
The following two text books provide discussions of memory requirements for computers: John L. Hennessy et al., "Computer Architecture-A Quantitative Approach", (Morgan Kaufmann Publishers, Inc., San Mateo, Calif., 1990); and Stephen B. Furber, "VLSI RISC Architecture and Organization", (Marcel Dekker, Inc., New York, N.Y., 1989), which are incorporated herein by reference. The following paragraphs include a summary from these text books concerning the state-of-the-art related to the present invention.
Memory latency is typically described using two measures: access time and cycle time. "Access time" is the time between when a read is requested and when the desired data arrives, while "cycle time" is the minimum time between requests to memory.
Using faster memory devices is the obvious way to improve not only memory, but memory bandwidth as well. Memory bandwidth is defined as how fast information can be supplied once the flow has started; it is the product of the rate of data transfer and the amount of data in each transfer, and is usually expressed in millions of bytes per second (Mbytes/s). Unfortunately, using faster memory has a direct impact on cost; the faster parts cost more. In the past, this cost was acceptable in certain supercomputers, but other classes of machines were constrained to use economical bulk memory technology. In most cases, this currently means using Dynamic Random Access Memory (DRAM) devices.
DRAMs are implemented in a way that exposes their internal structure, which is typically a near-square array of bits. A particular bit is specified by its row and column in the array. In the 1970s, as DRAMs grew in capacity, the cost of a package with all the necessary address lines became an issue. The solution was to multiplex the address lines, thereby cutting the number of address pins in half. The top half of the address comes first, during the "row-access strobe", or RAS. This operation is followed by the second half of the address during the "column-access strobe", or CAS. These names come from the internal chip organization, for memory is organized as a rectangular matrix addressed by rows and columns.
An additional requirement of DRAMs derives from the property signified by its first letter D for "dynamic." A "refresh" operation is required with DRAMs in order to maintain the information stored at each memory location due to the circuitry used. Refresh is done periodically by writing back data after it is read. Because of this refresh operation, every DRAM must have every row accessed within a certain time window, such as 2 milliseconds, or the information in the DRAM may be lost. This requirement means that the memory system is occasionally unavailable because it is sending a signal telling every chip to refresh. The time cost of a refresh is typically a full memory access (RAS and CAS) for each row of the DRAM. Since the memory matrix in a DRAM is likely to be square, the number of steps in a refresh is usually the square root of the DRAM capacity. The cycle time for DRAMs is therefore the access time plus the refresh time.
DRAM access times are divided into row access and column access. During each row access a DRAM will usually store one or more column bit locations in that row. This row is usually the square root of the DRAM size (e.g., 1024 bits for 1 Mbit, 2048 for 4 Mbits, and so on). DRAMs also come with optional timing signals that allow repeated column accesses to the memory after a single row-access time. These timing signals allow for information to be read out of a DRAM in one of several optimal ways that can optimize data retrieval.
There are three data retrieval optimization modes: nibble mode, page mode and static column mode. In "nibble mode", the DRAM can supply three extra bits from sequential locations for every row access. Contrastingly, by changing column address in "page mode", multiple random bits can be accessed in the buffer until the next row access or refresh time. "Static column mode" is very similar to page mode, except that it is not necessary to hit the column-access strobe line every time the column address changes. The static column mode has been given the acronym SCRAM, for static column DRAM.
Starting with conventional 1-Mbit DRAMS, most chips can perform any of the three modes. The desired optimization mode is selected at the time the chip is packaged by choosing which pads to wire-up as specified by the manufacturer. These modes change the definition of cycle time for DRAMS.
The advantage of these optimization modes is that they use the circuitry already on the DRAMS, adding little cost to the system while achieving almost a fourfold improvement in bandwidth. For example, nibble mode was designed to take advantage of the same program behavior as interleaved memory. The chip reads four bits at a time internally, supplying four bits externally in the time of four optimized cycles. Unless the bus transfer time is faster than the optimized cycle time, the cost of four-way interleaved memory is only more complicated timing control. Page mode and static column mode are also used to get even higher interleaving with slightly more complex control.
Thus, it is expected that most main memory systems in the future will use such optimization techniques to reduce the CPU-DRAM performance gap. Unlike traditional interleaved memories, there are no disadvantages using these DRAM modes as DRAMs scale upward in capacity, nor is there the problem of the minimum expansion increment in main memory.
Presently, main memory is expanded by adding DRAMs mounted on "single in-line memory modules" (SIMM). SIMMs are available off-the-shelf for most personal computers, workstations, and the like. Typically, these systems have main memory requirements in the range of 1-32 Mbytes. However, shared main memory multiprocessing systems have much greater main memory requirements.
What is desired is a faster, still higher memory capacity and more physically compact SIMM to meet present and future computer requirements.